70 ns access, 128K x 8 — the read-cycle ceiling
The CY62128DV30LL-70ZAXI is a 1 Mbit asynchronous SRAM from Infineon's MoBL low-power series, organized 128K x 8 with a 70 ns access time. That 70 ns figure sets the fastest read cycle the bus master can run without inserting wait states — at a 10 MHz bus clock (100 ns period) the SRAM responds within the first cycle, so no extra wait penalty.
Package and board-fit note
Housed in a 32-TFSOP (0.465-inch body width, 11.80 mm) — the same footprint as the industry-standard 32-TSOP. The 0.50 mm pin pitch and surface-mount leads suit a two-layer board if the decoupling caps sit close to the supply pins; a four-layer stack with a dedicated VDD plane is better for noise margin on the parallel bus. Write cycle time matches read at 70 ns (word and page mode), so the bus timing is symmetrical — no need to stretch the write strobe beyond the read pulse width.