MoBL 1 Mbit async SRAM — 70 ns access, byte-wide bus, industrial temp
The Infineon CY62128DV30L-70SI is a 1 Mbit asynchronous SRAM from the MoBL® series, organized as 128K x 8 bits with a 70 ns access time.
70 ns access — what it means for bus timing
The 70 ns write cycle time is symmetrical, so the bus timing budget is the same for both read and write operations.
128K x 8 organization — byte-wide fit
The 128K x 8 organization presents an 8-bit data bus. This directly matches 8-bit MCUs and DSPs without external byte-lane steering logic.
The 32-SOIC (0.445" body width) is a surface-mount footprint common in industrial PCBs; it is not a fine-pitch BGA, so hand rework and inspection are straightforward.
RoHS non-compliant — legacy solder finish
It cannot be used in a lead-free reflow process without a RoHS exemption or waiver. For new designs requiring RoHS compliance, a lead-free variant from the MoBL family should be selected. For legacy production lines that still run SnPb solder, this part is a direct fit.