Zero delay buffer with LVPECL input and 1:10 LVCMOS fanout
The CY29658AI is a PLL-based zero delay buffer from Infineon that accepts a single LVPECL input and distributes it to ten LVCMOS outputs with matched edge placement. The 200 MHz maximum frequency covers most FPGA, ASIC, and processor clock trees in telecom, networking, and industrial control equipment.
Supply flexibility and temperature grade
Operates from either a 2.5V rail (2.375V to 2.625V) or a 3.3V rail (3.135V to 3.465V), letting the same BOM position serve designs with different core voltages.
Package and footprint for layout planning
Housed in a 32-TQFP with a 7x7 mm body (supplier device package 32-TQFP (7x7)). The 0.80 mm pitch is routable on a four-layer board without blind vias; the exposed pad (if present) should be stitched to ground plane with at least nine thermal vias to keep the PLL junction temperature within spec.
Lifecycle and compliance posture
The part is RoHS non-compliant, so designs destined for EU or similar markets may need an exemption or a lead-free alternative.