DDR clock generator with PLL and 18 outputs
The Cypress CY28347ZCT is a processor-specific clock generator built around a PLL, designed to produce clean, low-jitter clock signals for DDR memory systems. It accepts a single clock input and fans it out to 18 clock outputs, with a maximum output frequency of 200 MHz. The part integrates two PLL circuits, allowing it to generate two independent clock domains from one reference — useful for separating the memory controller clock from the I/O or chipset clock on a motherboard or server blade. The input and output signals are differential (Yes/Yes), so the part works with LVDS or LVPECL-level clocks. That differential signalling keeps jitter low across the board, which is what DDR timing margins depend on. The 1:18 input-to-output ratio means one reference clock feeds up to 18 loads — DIMM slots, PCH, or other clock sinks — without needing external fanout buffers.
The CY28347ZCT operates on two supply ranges: 2.375 V to 2.625 V for the PLL core, and 3.135 V to 3.465 V for the output buffers.
The product status is Active. No direct pin-compatible second source is confirmed in the record.