PLL-based clock distribution in a 16-SOIC footprint
The Cypress CY23S08SC-3 is a PLL-based zero delay buffer that takes a single LVCMOS or LVTTL input and distributes it to eight LVCMOS outputs at up to 140 MHz. The internal PLL aligns the output edges to the input, eliminating propagation delay through the buffer — useful when clock skew across multiple loads needs to stay tight. This is a single-circuit device with a 1:8 fanout ratio, so one input drives eight clock lines without external fanout logic.
The 140 MHz maximum frequency is the upper bound for the clock signal this buffer can cleanly pass.
Commercial temp range — indoor use only
The 16-SOIC package is a standard footprint, easy to hand-rework or automated-place.
Note the RoHS non-compliant status — if your assembly line requires RoHS, verify your exemption or look for a lead-free variant.