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Infineon Technologies CY23FS04ZC — Clock & Timing ICs
Infineon Technologies

CY23FS04ZC Zero Delay Buffer, 166.7 MHz, 16-TSSOP

MPNCY23FS04ZC
End of Life

Cypress Failsafe™ CY23FS04ZC Zero Delay Buffer, 166.7 MHz max, 3:4 LVCMOS I/O, PLL with bypass, 16-TSSOP, 0°C to 70°C commercial temp.

$3.22Ref. price · indicative, final on quote
CY23FS04ZC datasheet
Packaging16-TSSOP (0.173", 4.40mm Width)
StockContact for availability
MOQ1 pcs
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Specifications

CY23FS04ZC Technical Specifications
ParameterValue
TypeZero Delay Buffer
SeriesFailsafe™
Mounting typeSurface Mount
Voltage2.375V ~ 2.625V, 3.135V ~ 3.465V
Frequency166.7MHz
Operating temperature0°C ~ 70°C (TA)
PLLYes with Bypass
InputLVCMOS, LVTTL, Crystal
OutputLVCMOS
PackageBulk
Case16-TSSOP (0.173\", 4.40mm Width)
Divider (Multiplier)No/No
Number of circuits1
Ratio - Input:Output3:4
Differential - Input:OutputNo/No

Product details

What this zero-delay buffer does for your clock tree

The Cypress CY23FS04ZC is a Failsafe™ zero-delay buffer designed to distribute a clean reference clock across a PCB with minimal skew between outputs. It integrates a PLL that can be bypassed, giving the designer a choice between jitter cleaning (PLL engaged) or a low-latency feed-through path (bypass mode). The part accepts LVCMOS, LVTTL, or a crystal input and delivers up to four LVCMOS outputs from a single reference, with a maximum output frequency of 166.7 MHz.

166.7 MHz ceiling and the 3:4 fanout

The 166.7 MHz maximum frequency sets the upper bound for the clock tree this part can serve. The 3:4 input-to-output ratio means three input pins feed four output clocks.

PLL with bypass — when to use each mode

The PLL-with-bypass feature is the main decision point. With the PLL engaged, the part phase-aligns its outputs to the input reference and filters jitter on the incoming clock. This is the mode to use when the reference comes from a noisy source like an oscillator on a long trace or a connector. In bypass mode, the PLL is shut down and the input clock passes through with minimal added delay — useful when the reference is already clean and you only need fanout, or during system bring-up to isolate PLL-related timing issues.

Supply rails and temperature range

The CY23FS04ZC operates from a 2.375 V to 2.625 V supply or a 3.135 V to 3.465 V supply, covering two common logic supply voltages in digital systems.

Package and footprint

Housed in a 16-pin TSSOP package with a 4.40 mm body width, this part fits a standard surface-mount footprint.

Lifecycle and sourcing reality

The part is RoHS non-compliant per the ledger — verify your assembly line's solder profile and exemption requirements if you are in a RoHS-regulated jurisdiction.

Frequently asked questions

What is a zero delay buffer used for?

A zero delay buffer distributes a single reference clock to multiple loads with minimal skew between outputs. It uses a PLL to phase-align the outputs to the input, canceling propagation delay through the device and board traces. This is critical in systems where multiple ICs (FPGAs, ASICs, processors) need a synchronous clock with tight timing margins.

How does the CY23FS04ZC differ from a standard PLL?

A standard PLL generates a new clock frequency from a reference, often with multiplication or division. The CY23FS04ZC is a zero-delay buffer: it does not change the frequency (no divider or multiplier) but instead replicates the input clock across multiple outputs while canceling the delay through the device. The PLL inside is used for phase alignment, not frequency synthesis. It also offers a bypass mode that shuts down the PLL for a clean feed-through path.

What is the closest functional equivalent to CY23FS04ZC?

The Cypress CY2305SXI-1HT is a related zero-delay buffer in the same family, but with a 1:5 fanout ratio (versus 3:4), a 133.33 MHz maximum frequency, and an industrial temperature range of -40°C to 85°C. It operates from a 3.0 V supply only, unlike the CY23FS04ZC which supports both 2.5 V and 3.3 V rails. The CY2305SXI-1HT is not a direct pin-compatible replacement — verify the fanout and supply requirements before substituting.