133.33 MHz zero-delay clock distribution in a 16-TSSOP
The CY2309CZXC-1H is a Cypress zero-delay buffer and fanout buffer that takes one LVCMOS or LVTTL input and distributes it to nine LVCMOS outputs, with a maximum frequency of 133.33 MHz. It integrates a PLL that can be bypassed, letting the part either align output edges to the input for zero-delay operation or pass the clock straight through for test or low-jitter paths. The single 3V to 3.6V supply rail means it drops straight into a 3.3V clock tree without level translation — no extra regulator or level shifter needed on that rail.
1:9 fanout — how many loads it can drive
With a 1:9 input-to-output ratio, a single CY2309CZXC-1H can feed up to nine clock loads — typically FPGA banks, multiple ADCs, or a set of Ethernet PHYs — without needing an external fanout tree. The outputs are non-differential (single-ended LVCMOS), so it is a straightforward drop-in for single-ended clock distribution. If your design needs more than nine copies, you cascade two of these or move to a higher-fanout part.
PLL with bypass — when to use it
The PLL with bypass feature gives you two operating modes. In normal zero-delay mode, the PLL aligns the output edges to the input, compensating for buffer propagation delay so the clock arrives at the loads in phase with the source. In bypass mode, the PLL is shut off and the input passes straight to the outputs — useful for system bring-up, fault isolation, or when the input clock is already clean and you just need fanout without phase alignment. The part has no divider or multiplier, so the output frequency equals the input frequency in both modes.
If your system sees -40°C or +85°C ambient, the sibling CY2305SXI-1HT carries an industrial temperature range but only five outputs.
16-TSSOP — rework and layout notes
The 16-TSSOP package (4.40 mm width, 0.173" pitch) is a fine-pitch surface-mount part that reflows cleanly with a standard lead-free profile.
ROHS3 compliant per the listing.