PLL zero delay buffer at 133.3 MHz
The CY2308SI-1T is a PLL-based zero delay buffer from Infineon that regenerates an input clock with near-zero propagation delay between input and output edges. It accepts one of two clock inputs and distributes it to four outputs, all phase-aligned to the selected reference. Maximum output frequency is 133.3 MHz — adequate for PCI, Ethernet MAC, or DDR memory reference clocks in the 100–133 MHz range. The PLL locks to the input within a few milliseconds; the bypass mode feeds the input straight through for test or low-jitter paths.
Supply rail and temperature grade
Operates from a single 3V to 3.6V supply, so it drops directly onto a 3.3V rail without an extra regulator. Surface-mount assembly with a typical reflow profile works; note the RoHS non-compliant status (lead-based solder terminals) may require a process waiver in some production lines.
Active production — sourcing posture
Because it is RoHS non-compliant, buyers in EU or similar regulated markets should verify their exemption coverage before committing the line.