133.33 MHz zero-delay fanout with PLL bypass
The CY2305SXI-1T is a zero-delay buffer that fans out one clock input to five outputs at up to 133.33 MHz, with an integrated PLL that phase-aligns the outputs to the input — the zero-delay characteristic means the propagation delay from input to any output is nominally zero, so the downstream devices see the same clock edge timing as the source. The PLL includes a bypass mode: when bypass is asserted, the PLL loop is opened and the input clock passes through the buffer chain directly, preserving the source phase noise profile at the expense of losing the zero-delay alignment. This is useful when the reference clock is already clean and the system needs only the fanout, not the deskew.
No external regulators or level shifters are needed when the board already runs a 3.3V plane.
ROHS3 compliant, meaning all six restricted substances plus the four phthalates are below the threshold — no exemption-based restrictions that could complicate EU market access.