PLL-based zero delay buffer at 133.33 MHz
The CY2305SC-1T is a PLL-based zero delay buffer from Infineon that takes one clock input and distributes it to five outputs with near-zero propagation delay between input and output. Maximum operating frequency is 133.33 MHz, which covers common 100 MHz and 125 MHz reference clocks for Ethernet PHYs, FPGAs, and SoCs. The part is non-differential on both input and output — single-ended clock distribution only.
1:5 fanout in SOIC-8
The 1:5 input-to-output ratio means one device replaces five separate clock buffers or a larger fanout tree, saving board space and reducing part count. The 8-SOIC package (3.90 mm width) keeps the footprint small. Compared to the industrial-temperature sibling CY2305SXI-1HT, this SC variant is limited to 0°C to 70°C — not suitable for outdoor or engine-bay environments, but fine for office equipment, test gear, and indoor telecom.
Active production, RoHS non-compliant
Sourced per RFQ against your BOM quantity.