Active NVSRAM with 20 ns access — no battery backup needed
The Infineon CY14B104NA-ZS20XI is a 4 Mbit non-volatile SRAM organized as 256K x 16, with a 20 ns access time over a parallel interface. It combines the read/write speed of an SRAM with on-chip non-volatile storage — data is retained at power loss without a battery or supercapacitor, which simplifies the BOM and eliminates periodic battery replacement. The 16-bit wide data bus matches MCUs and MPUs with a 16-bit external memory controller directly — no byte-lane muxing needed. The 20 ns access time keeps the cycle time short enough for most 16-bit and 32-bit processors running at moderate clock speeds without wait-state insertion.
The write cycle time (word or page) is also 20 ns, matching the read access time for symmetric bus timing.
ROHS3 compliant (no exemptions), covering EU and similar regulatory requirements without restriction.