Reset timing and open-drain output
The 140 ms minimum reset timeout is long enough to let bulk capacitors on the supply rails charge and for oscillators to start cleanly, but short enough that the system does not sit idle for a noticeable fraction of a second on a brown-out recovery. The open-drain output lets you wire-OR the reset signal with other supervisors or a manual reset button using a single pull-up resistor to the logic supply. Because the output is active low, the reset line is held low during the fault and timeout period; when all rails are good and the timer expires, the output goes high-impedance and the pull-up brings it high. This is the standard reset polarity for most MCUs and SoCs, so no inversion logic is needed.
The SOT-23-6 package dissipates only microwatts in normal operation, so self-heating is negligible.
ROHS3 compliant per the listing.