Reset timeout: 100ms minimum — why it matters
The 100ms minimum reset timeout gives the system power supply and oscillator time to stabilise before the processor is released from reset. This is a fixed, internally generated delay — no external capacitor needed. For most MCUs and simple SoCs, 100ms is adequate. If your design requires a longer delay for a large bulk capacitor to charge or a crystal to start, you would need a supervisor with a programmable or longer fixed timeout.
Push-pull output — no pull-up resistor on the BOM
The push-pull, totem-pole output actively drives the reset line high or low. For an active-low reset (the MAX6326UR29+T asserts reset low), the output pulls low when the supply is below threshold, and pulls high when the supply is good. This eliminates the external pull-up resistor that an open-drain supervisor would need, simplifying the layout and reducing component count. It also provides faster rise times on the reset line, which can be important for devices with a fast reset-release requirement.
The MAX6326UR29+T comes in a SOT-23-3 package (also known as TO-236-3 or SC-59). This is a three-pin surface-mount package.
For dual-sourcing resilience, the SOT-23-3 footprint is shared by many pin-compatible supervisors from other manufacturers — a direct cross-reference can be evaluated during BOM review.