It uses an R-2R ladder architecture and communicates over an I²C interface.
The 6 µs typical settling time to ±½ LSB defines how fast the output can move from one code to another. For a full-scale step, the output settles in 6 µs typical.
Package and supply — board-level fit
Both analog and digital supply pins run from the same 5 V rail.
Linearity error — INL and DNL
The integral non-linearity (INL) is specified at ±1.5 LSB maximum, and the differential non-linearity (DNL) at ±1 LSB maximum. For an 8-bit DAC, ±1.5 LSB INL means the actual output can deviate from the ideal straight line.
It is ROHS3 compliant.
