The LT1762EMS8-3.3#PBF: The 0.4 V maximum dropout at full load means the input rail needs to stay above 3.7 V to keep the output in regulation; below that headroom the output follows the input minus dropout. Power-supply rejection ratio is 65 dB at 120 Hz — this is the line-frequency ripple attenuation figure. For a 1 Vpp ripple on the input at 120 Hz, the output sees roughly 560 µVpp; that matters when the LDO feeds an analog front-end or a precision reference. Input voltage range extends to 20 V maximum, so the part survives 12 V and 15 V rails with margin. The -40 to +125 °C operating temperature range covers industrial and automotive-adjacent environments — the junction temperature limit is the same 125 °C, so thermal derating starts at the ambient ceiling.
Protection set and control interface
On-chip protection includes over-current limiting, over-temperature shutdown, and reverse-polarity protection — the reverse-polarity clamp means a reversed input rail does not forward-bias the internal pass device, which is a common failure mode on unipolar LDOs without it. An Enable pin lets the regulator be shut down externally; when pulled low the output goes to high-impedance and the quiescent current drops to near-zero, useful for sequenced power-up or low-power sleep modes.
Housed in an 8-MSOP (3.00 mm width, 0.118-inch pitch), the package footprint is shared with the 8-TSSOP outline — the same land pattern serves both. Surface-mount assembly with tube delivery; the MSOP body is low-profile enough for mezzanine or tight-height enclosures.