It uses Maxim's NVSRAM technology, which stores the SRAM contents to an internal EEPROM array on power-down and restores them on power-up — no battery, no external supervisor, no lithium cell to replace or dispose of. The 150 ns access time and 150 ns write cycle time match the bus timing of many 8-bit microcontrollers and legacy CPLD-based memory interfaces.
150 ns access — bus timing fit
Access time is 150 ns; write cycle time is also 150 ns.
