8-channel 16-bit DAC in a 4×4 mm LFCSP
The AD5668BCPZ-1-RL7 packs eight 16-bit voltage-output DACs into a 16-lead LFCSP-WQ measuring 4×4 mm — one of the densest channel-to-footprint ratios in the Analog Devices denseDAC family. Each channel settles to 16-bit accuracy in 7 µs typ, so a full eight-channel update cycle completes in under 60 µs, leaving headroom for the SPI bus overhead and the downstream amplifier settling. The String DAC architecture delivers inherent monotonicity: the ±1 LSB max DNL guarantee means every code step produces a positive voltage increment, which matters for closed-loop control loops that cannot tolerate non-monotonic transfer curves. The ±8 LSB max INL is the integral linearity error across the full output range — at 16 bits that is roughly 0.012 % of full scale, adequate for most industrial set-point and trim applications.
Supply flexibility and reference options
No separate VREF pin is required — the internal reference is enabled by default, but an external reference can override it per the REF bit in the control register. The buffered voltage output swings rail-to-rail on each channel, limited only by the output amplifier's headroom near the supply rails. The SPI/DSP serial interface supports daisy-chaining multiple AD5668 devices on a single three-wire bus — the SDO pin echoes the input shift register data, so a microcontroller can update 16, 24, or more channels with one CS strobe. The 16-bit data word carries the channel address and the DAC code, so no external address lines are needed.
Industrial temperature range and package
The 16-LFCSP-WQ package has an exposed paddle on the bottom — the datasheet recommends soldering it to a PCB copper plane for thermal management, though the 7 µs settling time and 8-channel simultaneous update keep the die temperature rise modest at typical update rates.