Altera EPM570ZF256C7N — FPGA / CPLD & Programmable Logic
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Altera / FPGA / CPLD & Programmable Logic

Altera EPM570ZF256C7N MAX II CPLD, 440 macrocells, 160 I/O

MPN EPM570ZF256C7N
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Altera MAX® II CPLD, EPM570ZF256C7N, 440 macrocells, 160 I/O, 9 ns tpd, 1.8 V core, 256-MBGA package, 0°C to 85°C operating temperature.

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Full Technical Specifications

11 Parameters
EPM570ZF256C7N specifications
Parameter / AttributeSpecification / Value
SeriesMAX® II
MountingSurface Mount
Programmable typeIn System Programmable
Voltage supply - internal1.71V ~ 1.89V
Operating temperature0°C~85°C(TJ)
PackageBulk
Number of i (O)160
Case256-TFBGA
Number of macrocells440
Delay time tpd(1) max9 ns
Number of logic elements (Blocks)570
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Technical Details & Description

440 macrocells, 9 ns pin-to-pin — the glue-logic sweet spot

The EPM570ZF256C7N is a MAX® II CPLD from Altera, packing 440 macrocells and 570 logic elements in a 256-MBGA (11x11 mm) footprint. With 160 user I/O and a 9 ns tpd(1) max propagation delay, it handles address decoding, bus bridging, and state-machine control at speeds that keep up with most 100 MHz-class processors without wait states.

I/O count and package — what fits on the board

The 256-TFBGA (11x11 mm, 0.8 mm ball pitch) gives you 160 available I/O — enough for a 32-bit data bus plus control signals and a handful of chip selects.

Frequently asked questions

What is the closest functional second-source for EPM570ZF256C7N?

The peer 5M570ZF256I5N (MAX V series) offers the same 440 macrocells and 9 ns tpd in a similar 256-MBGA package, but with an industrial temperature range (-40°C to 100°C) and 159 I/O. The ball map and footprint are not guaranteed identical — confirm the PCB layout before substituting.

What series does EPM570ZF256C7N belong to?

It is part of the MAX® II family, Altera's low-power, instant-on CPLD series with in-system programmability.

EPM570ZF256C7N
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