The ASEMDC2-LR: The silicon resonator inside replaces the traditional AT-cut quartz blank — it starts faster, tolerates shock and vibration better, and does not require a matching LC network to get the part into a tight frequency tolerance. The ultra-thin 0.90 mm profile makes it a direct alternative to crystal-and-PLL combinations where vertical board space is the binding constraint, such as a compact network switch line card or an embedded compute module with tight stack height.
Frequency options and CMOS output interface
The part ships in multiple frequency variants spanning two output tiers: 100 MHz, 106.25 MHz, 125 MHz, and 156.25 MHz in the primary tier, and 25 MHz, 50 MHz, 100 MHz, 125 MHz, and 156.25 MHz in the secondary tier. These cover the most common Ethernet reference frequencies and the standard PCIe Gen-1/Gen-2 clock rates without requiring a custom factory trim.
Supply, stability, and temperature grade
The maximum supply current is 32 mA when the output is active and 23 mA when disabled, so the enable pin is a legitimate power-management tool on battery-backed or thermally constrained designs. The VFQFN with exposed paddle requires a thermally aware footprint — the pad should be soldered to the board plane, not left floating, to keep junction temperature in check at full supply current.
It is quoted to order against BOM quantities through independent distribution; availability and current lead times are confirmed at RFQ.