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Toshiba Semiconductor 74VHC9273FT — Discrete Semiconductors

Toshiba 74VHC9273FT D-Type Flip-Flop, 20-TSSOPB, 100 MHz

MPN74VHC9273FT
End of Life

Toshiba Semiconductor 74VHC series D-Type flip-flop, 74VHC9273FT, 8-bit, positive edge trigger, non-inverted output, 20-TSSOPB package, 100 MHz clock frequency, 2V to 5.5V supply.

$0.42Ref. price · indicative, final on quote
Packaging20-TSSOP (0.173", 4.40mm Width)
RoHSROHS3 Compliant
Series74VHC
Independent supplier — new & surplus stockAuthenticity-screened · ESD-safe packingListing updated Aug 2026

Specifications

74VHC9273FT specifications
ParameterValue
TypeD-Type
Series74VHC
Output typeNon-Inverted
Trigger typePositive Edge
MountingSurface Mount
Supply voltage2V ~ 5.5V
Current - quiescent4 µA
Current - output high, low8mA, 8mA
Clock frequency100 MHz
Operating temperature-40°C ~ 125°C (TA)
PackageTape & Reel (TR); Cut Tape (CT)
FunctionMaster Reset
Case20-TSSOP (0.173\", 4.40mm Width)
Input capacitance4 pF
Number of elements1
Number of bits per element8
Max propagation delay @ v, max CL12.1ns @ 5V, 50pF

Product details

20-TSSOPB footprint and board integration

The 74VHC9273FT comes in a 20-TSSOP (4.40 mm width) package, supplier device package 20-TSSOPB, which is a standard 0.65 mm pitch footprint. The narrow body means the PCB land pattern must be precise — a 0.30 mm pad width on a 0.65 mm pitch leaves only 0.35 mm clearance between adjacent pads, so the solder mask registration needs to be tight to avoid bridging during reflow. MSL level isn't stated in the spec, but for a standard CMOS logic part in a TSSOP package, MSL 1 is typical — no bake required before reflow as long as the floor life isn't exceeded. The package is surface-mount only, so it's pick-and-place ready with no through-hole work.

100 MHz clock and 12.1 ns propagation delay — timing closure check

The 100 MHz clock frequency is the maximum toggle rate for the flip-flop itself, but the real timing budget for a design is set by the 12.1 ns max propagation delay at 5V with a 50 pF load. That delay includes the clock-to-Q time plus the output rise time into the load capacitance — so if the next stage has a setup time of 3 ns, the available clock period at 100 MHz (10 ns) is already tighter than the prop delay plus setup. At 100 MHz, you're running right at the edge; derate to 80 MHz or lower for reliable operation across temperature and process corners. The 4 pF input capacitance is typical for a 74VHC input stage — it won't load the clock driver significantly, but in a high-fanout design with eight flip-flops sharing the same clock line, the total load is 32 pF plus trace capacitance, which starts to matter for clock skew.

At 2V operation, the 100 MHz clock rate is not guaranteed; the max frequency drops with supply voltage, so for low-voltage battery applications, expect a lower toggle rate. The -40°C to 125°C operating temperature range is the full industrial grade — this part can sit in an engine bay or a rooftop solar inverter without derating. The quiescent current is only 4 µA, so in a battery-backed system that spends most of its time idle, the flip-flop's own draw is negligible.

Active lifecycle and compliance documentation

No minimum order quantity restrictions beyond the reel increment.

Frequently asked questions

Will 74VHC9273FT drop into a board designed for 74VHC273FT without rewiring?

The 74VHC9273FT and 74VHC273FT share the same 20-TSSOPB package, same pin count, same positive-edge trigger, and same non-inverted output type. If the board was designed for the 273FT, the 9273FT is a drop-in replacement with wider temperature margin — just verify that the 1.1 ns slower prop delay doesn't violate your timing budget.