5.7 kVrms isolation, 4A/6A drive — what this gate driver is built for
The UCC21520ADW: It is designed to drive IGBTs, SiC MOSFETs, and GaN FETs in half-bridge, full-bridge, and multi-level converter topologies where the high-side switch floats on a fast-switching node. The 4A source and 6A sink output current charges the gate capacitance quickly enough for switching frequencies in the hundreds of kilohertz, while the matched 30ns maximum propagation delay on both channels simplifies dead-time management and reduces shoot-through risk in hard-switched bridges. The 100V/ns minimum common-mode transient immunity keeps the output state latched through the dv/dt of a SiC or GaN half-bridge switching event, which is the difference between a clean transition and a latch-up fault.
30 ns propagation delay — matched channels for balanced switching
Both channels share a 30ns maximum propagation delay, with pulse-width distortion max of 6ns.
16-SOIC footprint and supply range — layout and rail planning
The 16-SOIC (0.295", 7.50mm width) body with surface-mount termination is a common footprint shared by many TI isolated drivers, so a board layout for this part can often accommodate a pin-compatible alternate without a respin. The output supply range of 6.5V to 25V covers the typical gate-drive voltages for IGBTs (15V) and SiC MOSFETs (18V to 20V), and the 6.5V minimum is low enough to drive logic-level MOSFETs if the application needs it.
Approvals and compliance — CQC, CSA, UR, VDE
The UCC21520ADW carries approvals from CQC, CSA, UR, and VDE.