Hermetic JFET op-amp for harsh environments
It combines a 2 MHz gain-bandwidth product with a 3.4 V/µs slew rate, drawing 625 µA per amplifier from a 7 V to 36 V supply.
The 4 pA input bias current (typical) preserves signal integrity in high-impedance sensor interfaces — photodiode amplifiers, pH probes, piezoelectric transducers — where a bipolar op-amp's nanoamp bias would swamp the signal. For a JFET op-amp that is a moderate figure; designs requiring sub-500 µV offset should budget for trim or select a precision-grade alternative. The 7 V minimum supply span means this part does not run on a single 5 V rail — it needs at least ±3.5 V or a single supply above 7 V.
Package and temperature grade — design-in notes
The 8-CDIP package (0.300 inch body width, 7.62 mm) is a through-hole ceramic DIP. The through-hole mounting means the part is not a candidate for high-density SMT reflow assembly; it is socketed or hand-soldered into plated through-holes. The ceramic body also handles higher storage and operating temperatures than plastic, but the 125°C junction limit still governs derating — the 80 mA output current should be derated above 85°C ambient.