The 1 pA typical input bias current keeps offset errors negligible with high source impedance. Supply span runs from 4.4 V minimum to 16 V maximum.
The CMOS input stage holds the 1 pA bias current across temperature, so drift in high-impedance circuits stays predictable. If your BOM runs at 85°C junction or below, the derating margin is generous; above that, budget the typical offset shift from the datasheet curves.
Package and mounting — 8-TSSOP, surface-mount only
Supplied in a tube of 8-TSSOP devices. The 0.173" body width and 4.40 mm pitch are standard for this footprint family. Surface-mount assembly only — no through-hole variant exists.