Dual 4-input NAND gate in 14-DIP — 5 ns propagation delay
The SN74S20N is a Texas Instruments 74S-series dual 4-input NAND gate in a 14-pin DIP package. It operates from a 4.75V to 5.25V supply and is rated for the commercial temperature range of 0°C to 70°C. The 5 ns maximum propagation delay at 5V with a 50 pF load makes it suitable for high-speed TTL logic designs where signal timing is tight. Each of the two independent gates accepts four inputs, with a guaranteed low-level threshold of 0.8V and high-level threshold of 2V — standard TTL-compatible levels. Quiescent supply current is 8 mA maximum, and the output can source 1 mA or sink 20 mA.
5 ns propagation delay — what it means for the bus
The 5 ns delay at 5V, 50 pF is the headline timing spec. In a backplane or memory-address decode path, that delay sets the minimum setup time the next stage needs.
Active lifecycle — no last-time-buy pressure
No end-of-life notices or last-time-buy dates are recorded. ROHS3 compliant. For new designs, the 74S series is a mature logic family. If your BOM calls for a through-hole 14-DIP dual 4-input NAND gate, this part is available through independent distribution and quoted to order against an RFQ — no allocation risk typical of newer process nodes.
Package and mounting — through-hole 14-DIP
14-lead DIP with 0.300-inch body width and 7.62 mm row spacing. Through-hole mounting suits prototype boards, legacy PCB retrofits, and hand-assembled runs. The supplier device package is 14-PDIP.