What the 150 MHz clock and 4.5 ns propagation delay mean for your bus
It clocks at 150 MHz with a propagation delay of 4.5 ns at 3.3 V into 50 pF. That 4.5 ns is the time from clock edge to valid output on a loaded trace — it sets your setup-and-hold budget for the next stage. With 24 mA of symmetric output drive on each channel, this part can directly drive a moderate backplane or a bank of LED indicators without external buffers. The positive-edge trigger and non-inverted tri-state outputs make it a drop-in for address latching or register banking in a 3.3 V system where you need to share a bus without contention.
The 5 pF input capacitance per channel keeps the loading light on the upstream driver. If you are migrating a 3.3 V design down to 1.8 V core logic, this part stays on the BOM without a footprint change — the same 48-SSOP lands on the same board layout.
The quiescent current sits at 20 µA typical, so it does not add a meaningful idle-power burden in a battery-backed system. The 48-BSSOP body is 7.50 mm wide — the same footprint as a standard 48-SSOP — and the surface-mount profile suits reflow assembly without special handling.
No last-time-buy notice, no end-of-life window to manage.