Octal transparent latch for bus isolation and address strobing
The Texas Instruments SN74LVC373ADW is an octal D-type transparent latch with tri-state outputs, part of the 74LVC low-voltage CMOS family. It holds eight bits of data when the latch-enable (LE) signal goes low, while the output-enable (OE) pin puts the bus outputs into high-impedance state for shared data lines. The 1.5ns typical propagation delay keeps address-latching and bus-isolation paths clean in 3.3V and 1.8V systems without adding wait states.
The 1.65V to 3.6V supply range covers both legacy 3.3V buses and modern 1.8V core logic, so the same BOM line works across a voltage transition without a level shifter. ROHS3 compliance means no Pb-free reflow concerns on standard assembly lines.
Package and board-level footprint
Housed in a 20-SOIC package with 0.295-inch (7.50mm) body width, surface-mount only. The 1.27mm pin pitch is standard for SOIC-20, so the PCB footprint matches any generic SOIC-20 land pattern. No thermal pad or exposed paddle — standard FR-4 with 0.5oz copper handles the dissipation at 24mA per output without thermal concerns.
Lifecycle and sourcing posture
Listed as Active — no last-time-buy or obsolescence risk. The ROHS3 compliance is current and verified.