Dual XOR gate for board-level glue logic
The 3.6ns propagation delay at 5V (50pF load) keeps timing closure manageable in moderate-speed digital buses up to roughly 50 MHz.
The 1.65V to 5.5V supply covers the common digital rails: 1.8V for low-power SoCs, 3.3V for most MCU and FPGA banks, and 5V for legacy TTL or industrial interfaces. No separate regulator or level shifter is needed if the supply matches one of those voltages. The 10µA maximum quiescent current means the gate adds negligible standby draw in battery-powered designs.