16-bit transparent latch for mixed-voltage buses
It is designed for address/data latching in memory interfaces, I/O expansion, and bus isolation where two independent 8-bit latches (circuit 8:8) share a single 48-SSOP package.
2.1 ns propagation delay — timing margin for fast buses
The 2.1 ns propagation delay is the key timing spec for this latch. In a 50 MHz bus with 10 ns cycle time, 2.1 ns leaves 7.9 ns for setup, hold, and skew — comfortable margin. The 24 mA output drive handles heavily loaded backplanes or multiple fan-out without external buffers. Compare this to the through-hole 74FCT573APC, which manages 8.5 ns propagation delay and 15 mA output drive over a 0°C to 70°C range — the SN74LVC16373ADL is faster, drives harder, and covers the full industrial temperature range.
Package and footprint — 48-SSOP with 0.295" body width
Surface-mount assembly with a standard SSOP footprint.