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Texas Instruments SN74LV161AD — DC-DC Power Modules

SN74LV161AD 4-bit synchronous binary counter, 95 MHz

MPNSN74LV161AD
End of Life

Texas Instruments 74LV-A series SN74LV161AD, 4-bit synchronous binary counter, positive edge triggered, asynchronous reset, 95 MHz count rate, 2 V to 5.5 V supply, -40°C to 85°C, 16-SOIC surface mount package.

$1.0Ref. price · indicative, final on quote
Packaging16-SOIC (0.154", 3.90mm Width)
StockContact for availability
MOQ1 pcs
  • 100% new & originalTraceable channels only — no refurbs, no pulls, no remarked parts.
  • Date & lot codes on quoteStated per line before you commit; label photos on request.
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Specifications

SN74LV161AD Technical Specifications
ParameterValue
Series74LV-A
Logic typeBinary Counter
Trigger typePositive Edge
Mounting typeSurface Mount
Voltage2 V ~ 5.5 V
Operating temperature-40°C ~ 85°C
ResetAsynchronous
TimingSynchronous
PackageTube
DirectionUp
Count rate95 MHz
Case16-SOIC (0.154\", 3.90mm Width)
Number of elements1
Number of bits per element4

Product details

What this 4-bit counter is and where it fits

The Texas Instruments SN74LV161AD is a 4-bit synchronous binary counter from the 74LV-A family, designed for general-purpose counting, frequency division, and timing-chain applications in digital logic systems. It counts up on each positive edge of the clock input and includes an asynchronous reset that forces all outputs low regardless of the clock state. The part operates from a 2 V to 5.5 V supply, making it compatible with both 3.3 V and 5 V logic rails — a common requirement when bridging legacy and modern digital buses. With a count rate of 95 MHz, it handles fast clocked counters in microcontroller peripheral glue, programmable logic interface, or test equipment dividers.

95 MHz count rate — what it means for timing margin

The 95 MHz count rate is the maximum clock frequency at which the counter reliably increments. In a 3.3 V system, propagation delays through the counter and any cascaded stages eat into the timing budget; at 95 MHz the clock period is about 10.5 ns, so you need to account for the counter's own propagation delay plus setup time of the next stage. For most microcontroller or FPGA interfaces running below 50 MHz, this part leaves comfortable margin. If you are cascading multiple counters for wider bit widths, the cumulative delay may limit the top speed — a single-stage 4-bit counter at 95 MHz is straightforward, but a 16-bit chain of four devices will need careful clock distribution.

Supply range and logic-level compatibility

The 2 V to 5.5 V supply range is a practical advantage: it runs from a 3.3 V rail in a mixed-voltage design without level shifters on the counter outputs, and it can also operate at 5 V for TTL-compatible legacy systems. The 74LV-A family is specified with LVCMOS input thresholds, so at 3.3 V the VIH minimum is typically 0.7 × VCC (about 2.3 V), which is easily driven by a 3.3 V microcontroller GPIO. At 5 V, the thresholds shift proportionally. This part is a clean drop-in for 3.3 V logic designs that need a synchronous counter.

Temperature grade and deployment environment

Rated for -40°C to 85°C, the SN74LV161AD covers industrial temperature environments — outdoor telecom cabinets, factory-floor PLCs, motor-drive control boards, and automotive cabin applications (non-AEC-Q100, but the range suits many under-hood-adjacent zones). The 16-SOIC package is a standard surface-mount footprint, easy to hand-assemble or reflow, and widely second-sourced for board-level repairs.

Lifecycle and sourcing posture

The SN74LV161AD is listed as Active on TI's product status, with no announced end-of-life or last-time-buy window. It is ROHS3 compliant. For a BOM line that needs a synchronous 4-bit counter with asynchronous reset, this part is a stable, long-availability choice. Pricing and stock are confirmed at quote time through independent distribution — sourced to order against an RFQ.

Frequently asked questions

Is SN74LV161AD compatible with 3.3 V logic?

Yes. The 2 V to 5.5 V supply range includes 3.3 V operation. At 3.3 V the input thresholds are LVCMOS-compatible, so a 3.3 V microcontroller or FPGA can drive the clock and reset pins directly without level translation.