Dual JK flip-flop for 5V logic chains
The Texas Instruments SN74LS73AN is a dual 1-bit JK flip-flop in the 74LS low-power Schottky family. Each flip-flop has a master-reset input for clearing the output asynchronously, and the trigger is negative-edge on the clock pin — meaning the output state toggles on the falling edge, not the rising one. The complementary outputs (Q and Q-bar) are available for both channels. This part is a direct fit for legacy 5V TTL logic designs where you need a simple toggle or divide-by-two function with a clean reset.
45 MHz clock and 20 ns propagation delay
The 45 MHz maximum clock frequency is the speed ceiling for cascaded stages — each flip-flop adds 20 ns of propagation delay at 5V with a 45 pF load. In a multi-stage counter or shift register, the total delay accumulates and limits the maximum chain length before timing violations appear. The 400 µA output-high and 8 mA output-low drive are standard for the 74LS family; they can sink enough current to drive one or two standard TTL loads but not a heavy bus or LED directly.
Supply and temperature — what fits
The supply range is 4.75 V to 5.25 V — a tight 5V ±5% rail. It belongs on a clean 5V logic rail, typically from a linear regulator or a 5V switching supply with low ripple.
Lifecycle and sourcing
No end-of-life notice or last-time-buy risk. It is a current, standard-logic part that remains widely specified for repair, legacy-equipment support, and new through-hole designs that need a reliable JK flip-flop.