Quad 2-input OR gate in 14-SOIC – 74HCT with TTL-compatible thresholds
This makes it a direct replacement for 74LS-series OR gates in existing 5 V designs without needing to re-terminate or adjust pull-up networks. The four independent OR gates each can source or sink 4 mA, and quiescent current is a maximum of 2 µA.
22 ns propagation delay – timing margin for 5 V buses
The maximum propagation delay is 22 ns at 5.5 V with a 50 pF load. In a 5 V logic chain, this sets the worst-case settling time for the OR gate's output. If the next stage has a setup-time requirement, the 22 ns figure must be included in the total path delay calculation. The 74HCT family's TTL-compatible inputs mean the SN74HCT32D can be driven directly by older 5 V TTL outputs without level translation.
This means it is still in regular production, with no announced end-of-life or last-time-buy window.
