Dual JK flip-flop with set and reset — 60 MHz toggle in a 16-SOIC
The SN74HC112DT: The 60 MHz maximum clock frequency suits moderate-speed counting, frequency division, and state-machine applications in industrial control, telecom, and general-purpose logic designs.
60 MHz clock and 21 ns propagation delay — timing budget considerations
The 60 MHz clock rating defines the maximum toggle rate for the flip-flop. At 6V supply with a 50 pF load, the propagation delay is 21 ns, which sets the timing margin for cascaded stages or synchronous counters. The input capacitance is 3 pF, a modest load for the driving gate. Quiescent current sits at 4 µA, making the part suitable for power-sensitive logic sections where the flip-flop is not continuously clocked.
Industrial temperature range and surface-mount footprint
Output current capability is 5.2 mA per pin for both high and low states, adequate for driving CMOS inputs or low-power LEDs.
Active production and compliance
It is ROHS3 compliant, meeting the current EU restriction requirements.