Single OR gate for the tightest power budgets
The Texas Instruments SN74AUP1G32DSF2 is a single 2-input OR gate from the 74AUP series, the industry's lowest-power logic family. It operates from 0.8V to 3.6V, making it a direct fit for battery-powered and multi-voltage designs where a standard 3.3V OR gate would draw too much idle current. The 500 nA maximum quiescent current means this gate can sit on a sensor interrupt line or a power-good combiner without draining the battery during sleep.
With a maximum propagation delay of 6.4 ns at 3.3V into a 30 pF load, this gate keeps combinatorial paths tight enough for most low-frequency control and status signals. It will not limit a 48 MHz SPI chip-select or a 1 MHz PWM enable. At lower supply voltages the delay increases, so if you are running the gate at 1.2V, budget closer to 20 ns — the datasheet curve is worth a look before signing off timing closure.
Package and footprint: 6-XFDFN (1 mm × 1 mm)
Housed in a 6-XFDFN package (supplier device package 6-SON, 1 mm × 1 mm), this part is surface-mount only.
Not qualified to AEC-Q100, so for under-hood or extended-temperature applications, look at the AUP family's automotive-grade siblings.