Hex inverter for low-voltage bus translation
The SN74ALVC04PWR is a six-channel inverter from TI's 74ALVC family, built for 1.65V to 3.6V supply rails. Each of the six gates inverts a single input, making it a straight drop-in for buffering or signal inversion on low-voltage logic buses. With a maximum quiescent current of 10 µA and 24 mA output drive at both high and low levels, it can fan out to multiple CMOS loads without additional buffering.
2.8 ns propagation delay at 3.3 V
Maximum propagation delay is 2.8 ns at 3.3 V with a 50 pF load. This is the figure that determines timing closure on fast parallel buses — a 2.8 ns gate adds roughly one-third of a clock period at 120 MHz. Input logic thresholds are specified as 0.7 V to 0.8 V low and 1.7 V to 2.0 V high, which are compatible with 1.8 V and 2.5 V logic families without external level shifters.
Active production, ROHS3, 14-TSSOP
No end-of-life notice or successor has been issued — production is current. The 14-TSSOP package (0.173" body width, 4.40 mm) is a common footprint for low-pin-count logic. Tape-and-reel and cut-tape options are available for both prototyping and volume assembly.