Quad 2-input NAND — 3 ns at 3.3 V
It operates from 1.65 V to 3.6 V and delivers a maximum propagation delay of 3 ns at 3.3 V with a 50 pF load. Output drive is 24 mA per channel, enough to fan out to ten or more LSTTL loads on a short PCB trace. Quiescent current maxes at 10 µA, making it suitable for battery-aware logic in portable or always-on subsystems.
The 1.65 V minimum lets this gate run directly from a 1.8 V core rail, while the 3.6 V maximum covers 3.3 V with margin. That means the same part works in a low-voltage FPGA interface and a 3.3 V peripheral bus without a level translator. Input logic thresholds scale with supply: low-level at 0.7 V to 0.8 V, high-level at 1.7 V to 2 V.
Timing budget — 3 ns at 3.3 V
The 3 ns max propagation delay at 3.3 V and 50 pF is the number to check against your clock-to-data setup margin. At lower supply voltages the delay increases — budget extra time if running from a 1.8 V rail. The 24 mA symmetrical output drive keeps edge rates clean into typical CMOS loads and short traces.
No last-time-buy or obsolescence risk.