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Texas Instruments SN74AC563N — Discrete Semiconductors

SN74AC563N D-Type Transparent Latch, 4.6ns, 20-DIP

MPNSN74AC563N
End of Life

Texas Instruments 74AC series SN74AC563N, D-Type Transparent Latch, 8:8 circuit, Tri-State output, Through Hole, 20-DIP (0.300", 7.62mm), 2V ~ 6V supply, 4.6ns propagation delay, 24mA output drive, -40°C ~ 85°C.

$1.88Ref. price · indicative, final on quote
Packaging20-DIP (0.300", 7.62mm)
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Specifications

SN74AC563N Technical Specifications
ParameterValue
Series74AC
Logic typeD-Type Transparent Latch
Output typeTri-State
Mounting typeThrough Hole
Voltage2V ~ 6V
Current - output high, low24mA, 24mA
Operating temperature-40°C ~ 85°C
Circuit8:8
PackageTube
Case20-DIP (0.300\", 7.62mm)
Independent circuits1
Delay time - propagation4.6ns

Product details

Octal transparent latch with tri-state bus hold

The Texas Instruments SN74AC563N is an octal D-type transparent latch in the 74AC logic family. When the latch-enable input is high, the Q outputs follow the D inputs; when low, the outputs latch the last data. The tri-state output control lets you isolate the latch from the bus, which is useful in shared-data-path designs like microprocessor memory interfaces or I/O port expansion. The 20-pin DIP package (0.300" body width) is a through-hole footprint that suits prototyping, legacy board repairs, or designs where vibration resistance matters more than board density. Industrial temperature range (-40°C to 85°C) covers factory-floor enclosures, outdoor telecom cabinets, and unheated storage.

Lifecycle and sourcing

The SN74AC563N is listed as Active with RoHS3 compliance. No end-of-life notice or last-time-buy schedule is in effect, so it remains a standard catalog item through TI's distribution channel. For BOM planning, this means no near-term requalification risk — you can freeze the line item without watching for a PCN.

Tri-state output: bus isolation without a separate buffer

The tri-state output enable (active-low) lets multiple latches share a common data bus. When the output enable is high, the outputs go high-impedance — the latch still captures data internally, but the bus sees no load. This is the standard architecture for memory address latches, peripheral I/O ports, and bidirectional data buffers where you need to park the outputs during a bus turn-around.

Frequently asked questions

What is the difference between SN74AC563N and SN74AC564N?

The SN74AC563N is a transparent latch (outputs follow inputs while latch-enable is high). The SN74AC564N is a flip-flop (edge-triggered register) — it captures data only on a clock edge. Both are octal, tri-state, 20-DIP, but the 564N is used where you need synchronous storage rather than transparent pass-through.

Is SN74AC563N a tri-state latch?

Yes, the SN74AC563N has tri-state outputs controlled by an active-low output-enable pin. When the output enable is high, the outputs go high-impedance, allowing multiple devices to share a common bus.