150 MHz D-type register with master reset — what the timing specs mean for the bus
The SN74ABT273DBR is an 8-bit D-type flip-flop from TI's 74ABT family, featuring a positive-edge clock trigger and an active-low master reset that clears all outputs asynchronously. The 150 MHz maximum clock frequency and 6.8 ns propagation delay at 5 V, 50 pF define the timing budget. The 32 mA source / 64 mA sink output drive handles heavily loaded data buses without external buffers, but the 7 pF input capacitance per channel adds up on a wide bus — account for it in the clock-tree fan-out calculation.
Package and footprint — 20-SSOP specifics
Housed in a 20-SSOP (5.30 mm body width, 0.209 inch pitch), surface-mount only. The supplier device package is the same 20-SSOP — no alternate package variant in this order code.
No NRND or last-time-buy flags in the record, so this part can be designed into new BOMs without near-term obsolescence risk. The 74ABT family has broad distribution coverage; the SN74ABT273DBR is a standard catalog item.