25 MHz core and dual ADC — what they mean for the BOM
The 25 MHz clock is fast enough to handle the sigma-delta decimation filter in real time while refreshing the LCD and managing a UART or SPI link to a host. The dual ADC architecture — two 24-bit sigma-delta channels plus an 8-channel 10-bit SAR — means this one chip replaces a separate AFE and a smaller MCU in a polyphase meter. The 72 GPIOs give you room for tamper detection, relay drivers, and a keypad matrix without a port expander.
Lifecycle and sourcing posture
Listed as Active. This part is sourced through independent distribution and quoted to order against an RFQ. Availability and current pricing are confirmed at quote time.
