Quad CMOS op-amp — 1.5 mA total supply, picoamp bias
Key features include a gain bandwidth product of 1.4 MHz, a slew rate of 1.1 V/µs, and an exceptionally low input bias current of 0.002 pA — typical for CMOS input stages and critical for high-impedance sensor interfaces. The output stage is push-pull rail-to-rail, allowing the output to swing within millivolts of either supply rail in single-supply designs. Supply span ranges from 4.75 V to 15.5 V, and each channel can source or sink 40 mA.
1.5 mA quiescent for four channels — what that means on the rail
Total supply current for all four amplifiers is 1.5 mA, which works out to roughly 375 µA per channel. In a battery-powered or multi-channel data-acquisition system, that quiescent draw is low enough to keep the thermal budget comfortable in a 14-SOIC without airflow. The 40 mA per-channel output current gives enough drive for modest loads — think driving an ADC input, a reference buffer, or a small relay — but not for heavy cable or 50-ohm back-termination. If you need more output muscle, plan on a separate buffer stage.
0.002 pA input bias — the so-what for sensor front ends
The CMOS input stage delivers a typical input bias current of 0.002 pA. That is essentially negligible for most practical circuits — a photodiode amplifier, pH probe buffer, or electrometer front end will see virtually no offset from bias current.