80 MHz Cortex-M3 — what it means for the design
The 80 MHz core with single-cycle multiply and hardware divide handles real-time control loops and protocol stacks without external memory. The 512 KB Flash is enough for a full TCP/IP stack plus application firmware; the 96 KB RAM supports moderate-sized data buffers. Designs that need more than 96 KB of working memory will require an external SRAM via the EBI/EMI interface.
Connectivity and I/O — a single-chip gateway
USB OTG, CAN, I²C, SPI, UART, and IrDA are on-chip. The 72 GPIOs in a 108-ball BGA leave room for a parallel LCD or external memory bus.