Six unidirectional channels in a 16-SOIC — what the pin count tells you
The Texas Instruments ISO6760LDWR is a capacitive-coupling digital isolator packing six unidirectional channels, all six configured as inputs on side 1 with no outputs on side 2. That 6/0 input-side count means every channel drives the same direction — there are no reverse-direction or bidirectional lanes. The 16-SOIC (7.50 mm width) body holds the six isolated forward paths plus the usual supply and ground pins, leaving no room for a second-side output bank. If your application needs any return-path isolation (side 2 driving back to side 1), this part won't cover it; you'd step to a part like the ISO6762FDWR with its 4/2 input/output split.
50 Mbps and 5000 Vrms — the throughput-versus-creepage tradeoff
At 50 Mbps the ISO6760LDWR sits in the mid-speed tier for capacitive isolators — fast enough for SPI clock rates up to 25 MHz (half-duplex) or parallel GPIO update streams, but not aimed at 100 Mbps+ Ethernet or LVDS links. The 5000 Vrms isolation rating is the reinforced-grade figure, suitable for mains-isolated interfaces in industrial drives, medical equipment, and grid-tied power systems where you need a 5 kV withstand test. Propagation delay is 20.5 ns max (both tpLH and tpHL), with pulse-width distortion held to 7 ns max — tight enough to pass a 20 MHz clock without duty-cycle skew eating into setup/hold margins. The 2.6 ns typical rise/fall edges are fast; plan series termination or controlled-impedance traces if the load is more than one gate input.
Common-mode transient immunity: 50 kV/µs minimum
The 50 kV/µs minimum CMTI is the spec that matters when this isolator sits between a noisy power stage and a controller. Motor-drive inverter nodes, GaN/SiC switching edges, and H-bridge mid-points generate common-mode voltage spikes that can couple through parasitic capacitance and corrupt data. At 50 kV/µs the capacitive barrier rejects those transients cleanly — no bit errors from a 600 V bus switching at 50 kHz with a 50 ns edge. If your system runs below 20 kV/µs common-mode slew, the headroom is generous; if you're pushing 100 kV/µs (fast SiC edges), you need a higher-rated isolator.
Split supply domains for level translation
The 1.8 V domain matches the I/O voltage of many modern MCUs and SoCs directly, saving a level-shifter IC. No isolated power is generated on-chip — each side needs its own local supply, and the barrier provides only signal isolation, not DC/DC conversion.
Temperature grade and environment
The 125°C ceiling includes engine-bay ambient plus self-heating; junction temperature stays within the silicon limit as long as the 16-SOIC's thermal resistance is respected. Surface-mount assembly with standard reflow profiles — no special handling beyond MSL precautions (verify the moisture sensitivity level on the reel label before bake decisions).
Lifecycle and sourcing reality
It's a standard TI catalog part, not a custom or short-lead-time special. The 16-SOIC package and Tape & Reel / Cut Tape options are standard for high-volume pick-and-place; there's no second-source alternate listed in the TI portfolio, so plan for single-source risk on this line item. If a dual-source strategy is required, the closest functional match is the ISO6760LNDWR — same channel count, data rate, and isolation rating — but verify pin compatibility against your layout before substituting.