Clock fanout for LVDS, LVPECL, and PECL lines
The Texas Instruments DS90LV110TMTC/NOPB is a 1:10 fanout buffer that accepts LVDS, LVPECL, or PECL inputs and delivers ten LVDS outputs. It runs from a 3V to 3.6V supply and handles clock rates up to 400 MHz. The differential input and output path (Yes/Yes per the spec) preserves signal integrity across the fanout tree. This part sits in the clock distribution chain of telecom line cards, data-acquisition backplanes, and any system that needs to split a high-speed reference clock to multiple ASICs or FPGAs without degrading edge rates.
400 MHz ceiling and what it means for your line rate
The 400 MHz maximum frequency covers most LVDS clock distribution up to gigabit-class serial links (e.g., 1 GbE, SFP+ reference clocks). If your design needs to fan out a 312.5 MHz or 156.25 MHz oscillator to ten destinations, this buffer has the bandwidth. The 1:10 ratio means one device replaces two 1:5 or three 1:4 buffers, consolidating BOM count and routing complexity. However, the ten outputs present a combined load that the upstream clock source must drive — check the input capacitance and drive strength of the preceding PLL or oscillator.
Supply and temperature — 3.3V rail, industrial range
The 3V to 3.6V supply range ties this part to a 3.3V rail. If your board runs 2.5V or 5V clock logic, you will need a local regulator or a different buffer. The -40°C to 85°C operating temperature covers industrial environments — outdoor telecom cabinets, factory-floor controllers, and base stations. The 28-TSSOP package (0.173" body width, 4.40 mm) is a fine-pitch surface-mount footprint that routes well on standard PCB stacks.
Active lifecycle and compliance
It is ROHS3 compliant, which covers the EU RoHS exemption list. The NOPB suffix confirms lead-free construction — no Pb in the solder finish. For new designs, there is no imminent obsolescence risk.