200 MHz fanout buffer — one input drives ten LVDS loads
The Texas Instruments DS90LV110ATMT/NOPB is a 1:10 fanout buffer that accepts a single differential input — LVDS, LVPECL, or PECL — and distributes it as ten LVDS outputs. The 200 MHz maximum frequency sets the ceiling for clock or data distribution in systems like telecom backplanes, FPGA clock trees, and high-speed data-acquisition front ends. The 1:10 ratio means a single device can replace a two-stage buffer tree, saving board area and reducing additive jitter from cascaded stages. Supply range of 3V to 3.6V lets it run directly from a nominal 3.3V rail with margin for ripple and regulation tolerance. Differential input and output paths throughout preserve signal integrity over the full temperature range.
Input flexibility — LVDS, LVPECL, or PECL accepted
The DS90LV110ATMT/NOPB accepts three common differential signalling standards on its single input: LVDS, LVPECL, and PECL. This cross-protocol compatibility is the part's main design-in advantage — it can sit between a PECL oscillator and an LVDS fanout tree, or buffer an LVPECL clock from an FPGA transceiver bank to multiple downstream LVDS receivers, without level-shifting resistors or a translator IC. The output is always LVDS, which keeps the fanout lanes at a consistent, low-swing standard that minimises EMI and power per link.
The ROHS3 compliance covers current European and global material restrictions, so no separate Pb-free waiver is needed.