Single-channel LVDS ReDriver with signal conditioning
It accepts CML, LVDS, or LVPECL inputs and outputs a clean LVDS signal, with built-in input equalization and output pre-emphasis to compensate for channel attenuation at data rates up to 3.125 Gbps. The 350 ps typical delay keeps added latency minimal for timing-critical links. Housed in an 8-WSON (3x3 mm) package with an exposed thermal pad, it operates from a 3V to 3.6V supply and draws 35 mA typical supply current.
3.125 Gbps lane speed and signal conditioning
The 3.125 Gbps data rate covers common serial standards like Gigabit Ethernet, SATA, and PCIe Gen1, making this ReDriver a fit for extending reach on FR4 backplanes or cable assemblies where the raw LVDS driver lacks swing margin. Input equalization compensates for high-frequency skin-effect losses, while output pre-emphasis boosts the first few bits after a transition to open the eye at the receiver. The 1.7 pF input capacitance keeps stub loading light on the upstream driver.
For a production BOM line, this part does not carry imminent obsolescence risk — it is a current, catalog-listed device from Texas Instruments.
Input flexibility: CML, LVDS, LVPECL
The ReDriver accepts three common differential signaling standards on its input — CML, LVDS, and LVPECL — and outputs a standard LVDS swing. This saves a level-shifter or translator when interfacing, for example, an LVPECL oscillator to an LVDS receiver, or a CML SerDes output to an LVDS backplane. The 3V to 3.6V supply range aligns with typical 3.3V backplane rails.
The 35 mA supply current is modest.