What this 60 V NexFET delivers
The package with exposed drain pad pulls heat into the PCB copper plane; the 156 W power dissipation at the case is the thermal limit when the pad is properly soldered to a thermal via array.
Total gate charge is 58 nC at 10 V. Input capacitance is 5070 pF at 30 V drain bias.
The 8-PowerTDFN (VSONP 5x6) has a 5 mm × 6 mm footprint with a large exposed drain pad on the bottom. The PCB land pattern should match the pad dimensions in the datasheet layout recommendation.
For dual-sourcing resilience, verify the Rds(on) and gate-charge differences against your loss budget before substituting.
