The Texas Instruments CDCM7005RGZT is a clock synchronizer and jitter cleaner built around a PLL that supports bypass mode. It accepts LVCMOS or LVPECL inputs and delivers LVCMOS or LVPECL outputs across a 3:10 input-to-output ratio, with a maximum operating frequency of 1.5 GHz. The part operates from a 3V to 3.6V supply and is rated over the -40°C to 85°C industrial temperature range, making it a fit for base stations, wireless infrastructure, and high-speed data converter clocking where phase noise and jitter budgets are tight.
PLL with bypass — why that matters for your clock tree
The PLL includes a bypass path, which means the device can pass a reference clock through without phase-locking when jitter cleaning is not needed. This is useful during system bring-up or when a clean external clock is already available. The differential input and output capability supports LVDS-like signalling for long PCB traces or backplane distribution, preserving signal integrity at 1.5 GHz.
Package and mounting — 48-VQFN with exposed pad
Housed in a 48-VQFN exposed-pad package measuring 7x7 mm.