800 MHz fanout buffer with wide input flexibility
Its input stage accepts CML, HSTL, LVDS, LVPECL, LVTTL, SSTL-2, and VML, so this single part can sit behind most high-speed serial interface standards without external level shifters. Outputs are LVCMOS or LVPECL, and the signal path is fully differential, which preserves edge integrity in noisy backplanes or long PCB traces.
The 24-VQFN package (4x4 mm) with exposed pad requires a thermal land on the PCB to pull heat from the die; the pad is electrically connected to the ground plane.
1:3 ratio vs 2:4 peer
Compared to the CDCLVP1204RGTR, which offers a 2:4 input:output ratio and 2 GHz max frequency, the CDCM1804RGET runs a 1:3 ratio at 800 MHz. The CDCLVP1204 also accepts LVCMOS, LVDS, LVPECL, and LVTTL, but omits CML, HSTL, SSTL-2, and VML. If your clock source is CML or SSTL-2, the CDCM1804RGET is the direct fit; for higher fan-out or 2 GHz rates, the CDCLVP1204RGTR is the alternative.
