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Texas Instruments CDCLVD2104RHDT — Clock & Timing ICs

CDCLVD2104RHDT Clock Buffer, 1:4 Fanout, 800 MHz

MPNCDCLVD2104RHDT
End of Life

Texas Instruments CDCLVD2104RHDT, Fanout Buffer (Distribution), 2 circuits, 1:4 input:output per circuit, LVCMOS/LVDS/LVPECL input, LVDS output, 800 MHz max, 2.375V-2.625V supply, -40°C to 85°C, 28-VQFN (5x5) exposed pad.

$11.19Ref. price · indicative, final on quote
Packaging28-VFQFN Exposed Pad
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Specifications

CDCLVD2104RHDT Technical Specifications
ParameterValue
TypeFanout Buffer (Distribution)
Mounting typeSurface Mount
Voltage2.375V ~ 2.625V
Frequency800 MHz
Operating temperature-40°C ~ 85°C
InputLVCMOS, LVDS, LVPECL
OutputLVDS
PackageTape & Reel (TR); Cut Tape (CT)
Case28-VFQFN Exposed Pad
Number of circuits2
Ratio - Input:Output1:4
Differential - Input:OutputYes/Yes

Product details

800 MHz fanout buffer with dual 1:4 trees

The CDCLVD2104RHDT from Texas Instruments is a dual fanout buffer that takes one input — LVCMOS, LVDS, or LVPECL — and distributes it to four LVDS outputs per circuit, with two independent circuits on the die. That means you can feed two separate clock domains from a single device, each getting a clean 1:4 split at up to 800 MHz. The differential input and output path is fully differential throughout, so common-mode noise on the clock line gets rejected rather than passed downstream.

Input flexibility saves a level translator

The input stage accepts LVCMOS single-ended signals as well as LVDS and LVPECL differential pairs. If your upstream oscillator or PLL puts out a 2.5V LVCMOS clock, you can feed it directly without an external level shifter — just one AC-coupling cap if the source is differential. The output is always LVDS, which is the standard for driving long PCB traces or backplane clock lines with low swing and good noise margin.

Industrial temperature range for outdoor and factory gear

Rated from -40°C to 85°C, this buffer fits telecom base stations, outdoor small cells, and industrial motor drives that see seasonal temperature swings. The 2.375 V to 2.625 V supply rail is tight — 2.5 V nominal — so make sure your regulator holds within that window across load and temperature; a 3.3 V rail needs a separate 2.5 V LDO.

Package and layout: 28-VQFN with exposed pad

The 28-VQFN (5x5 mm) package has an exposed thermal pad that must be soldered to a ground plane for both electrical return and heat sinking. The pad is the main thermal path — without a via array under it, the junction temperature climbs fast if you run both circuits at full 800 MHz into 50-ohm loads. Keep the decoupling capacitors within 2 mm of the supply pins; the datasheet layout example is worth following closely.

Lifecycle and sourcing

It is RoHS3 compliant.

Frequently asked questions

What is the equivalent of CDCLVD2104RHDT?

The closest functional peer is the CDCLVP1204RGTR, which is a single-circuit 2:4 fanout buffer with LVPECL outputs instead of LVDS. It accepts LVCMOS, LVDS, LVPECL, and LVTTL inputs and runs up to 2 GHz, but it has only one circuit and a different output type. If you need LVDS outputs and two independent 1:4 trees, the CDCLVD2104RHDT is the correct part.

Is CDCLVD2104 compatible with 3.3V input logic?

The supply voltage range is 2.375 V to 2.625 V, so the device itself runs on 2.5 V. The input accepts LVCMOS levels, but a 3.3 V LVCMOS signal will exceed the recommended input voltage range unless you AC-couple it or add a resistive divider. For direct DC coupling, keep the input swing within the 2.5 V supply rails.