1:4 LVDS fanout at 800 MHz – what it does
The CDCLVD1213RGTT is a single-channel fanout buffer that takes one differential input (CML, LVDS, or LVPECL) and distributes it to four LVDS outputs, with an optional divider stage. The 800 MHz maximum frequency covers common telecom and data-converter clock rates up to gigabit serial links. Supply voltage is 2.375V to 2.625V — a 2.5V rail with ±5% tolerance keeps the part in spec. The industrial temperature range suits base station, networking, and test equipment environments.
Input flexibility and output drive
Input accepts CML, LVDS, or LVPECL levels without external termination resistors for DC-coupled paths — the internal 100-Ω termination on the input pair handles the differential swing. Outputs are LVDS, which delivers 350 mV typical swing into a 100-Ω load, keeping EMI low on long backplane traces. The 1:4 fanout ratio means one clock source drives four receiver loads; the divider option lets you generate a sub-rate clock (e.g., half-frequency) from the same input. Both input and output paths are fully differential, so common-mode noise rejection is maintained through the buffer.
Package and footprint notes
Housed in a 16-VFQFN with exposed pad, 3 mm × 3 mm body. Surface-mount with standard reflow profiles.
Production status and ordering
ROHS3 compliant. Sourced to order against BOM quantities. No firm stock or lead-time claim here — confirm availability and current pricing through an RFQ.