What this LVDS fanout buffer does
The CDCLVD110AVFR is a 2:10 LVDS fanout buffer and multiplexer from Texas Instruments. It takes up to two LVDS clock inputs and distributes a selected input to ten LVDS outputs, all differential, with a maximum frequency of 1.1 GHz. The 2:10 ratio means one device can feed ten clock destinations from two selectable sources, reducing component count on high-speed serial backplanes or FPGA clock trees.
Supply and temperature range
Supply voltage is tight at 2.375V to 2.625V — this is a 2.5V nominal rail part. The regulator feeding it should be clean and low-noise; a 100 nF plus 10 µF decoupling pair per supply pin is the standard starting point.
Housed in a 32-LQFP (7x7 mm) with 0.8 mm pitch — a standard quad flat pack that routes easily on a four-layer board.
The part is ROHS3 compliant.